1. Field of the Invention
The present invention relates to a method and a circuit for driving a display device. More particularly, the present invention relates to a method and a circuit for driving a display device such that the display quality of an active matrix type liquid crystal display device, including active elements such as thin film transistors (TFTs), is less affected by variations of the average of the voltages applied to data lines included in such a display device.
2. Description of the Related Art
First, the fundamental configuration and the operational principles of a conventional digital driver will be described.
FIG. 1A shows a circuit section corresponding to one output of a conventional three-bit digital driver.
This circuit section corresponds to one of a plurality of data lines included in a liquid crystal display panel.
In the following description, this circuit section will be called a "unit driver circuit". The conventional three-bit digital driver includes the same number of unit driver circuits as that of the data lines included in the liquid crystal display panel.
As shown in FIG. 1A, the unit driver circuit includes: a sampling memory M.sub.SMP ; a holding memory M.sub.H ; and an output circuit section OPC.
The sampling memory M.sub.SMP samples three-bit digital image data in synchronism with the leading edge of a sampling pulse T.sub.SMP.
The holding memory M.sub.H retrieves the image data from the sampling memory M.sub.SMP and holds the data therein in synchronism with the leading edge of an output pulse LS which is synchronous with a horizontal synchronizing signal.
The output circuit section OPC selectively outputs one of eight different gray-scale voltages V.sub.0 through V.sub.7 to a data line DL.sub.n depending upon the value of the image data held in the holding memory M.sub.H. Herein, DL.sub.n denotes a data line on an n-th column. The gray-scale voltages V.sub.0 through V.sub.7 are supplied from the outside of unit driver circuit to the output circuit section OPC. The output pulse LS is supplied to the holding memory M.sub.H after the sampling of data has been completed in all of the unit driver circuits included in the digital driver. Herein, the sampling of data refers to a retrieval of the image data into the sampling memory M.sub.SMP in synchronism with the leading edge of the sampling pulse T.sub.SMP.
FIG. 1B shows a specific configuration of the output circuit section OPC shown in FIG. 1A. The output circuit section OPC includes: a decoder DEC for converting the three-bit image data into eight switch control signals S.sub.0 through S.sub.7 ; and analog switches ASW.sub.0 through ASW.sub.7 for receiving the corresponding switch control signals S.sub.0 through S.sub.7, respectively, and outputting the gray-scale voltages V.sub.0 through V.sub.7 corresponding to the switch control signals S.sub.0 through S.sub.7, respectively, to the data line DL.sub.n.
For example, if the value of the image data held in the holding memory M.sub.H is "4", only the switch control signal S.sub.4 of the eight switch control signals S.sub.0 through S.sub.7 which are output from the decoder DEC is activated. As a result, only the analog switch ASW.sub.4 of the eight analog switches ASW.sub.0 through ASW.sub.7 is turned ON. In this manner, the gray-scale voltage V.sub.4 input to the analog switch ASW.sub.4 is output to the data line DL.sub.n.
FIG. 2 shows the waveforms of respective signals in the case of alternating current (AC) driving a liquid crystal display panel. In FIG. 2, Hsync denotes a horizontal synchronizing signal, and POL denotes a signal representing either a time period during which the potential of a pixel electrode is charged to be positive with respect to a voltage V.sub.COM applied by a common electrode (hereinafter, such a time period will be referred to as a "positive drive time period") or a time period during which the potential of the pixel electrode is charged to be negative with respect to the voltage V.sub.COM applied by the common electrode (hereinafter, such a time period will be referred to as a "negative drive time period"). The signal POL will be called a "polarity signal".
V.sub.0, V.sub.2, V.sub.5 and V.sub.7 respectively denote the potentials of the gray-scale voltages V.sub.0, V.sub.2, V.sub.5 and V.sub.7 during the positive drive time period, while -V.sub.0, -V.sub.2, -V.sub.5 and -V.sub.7 respectively denote the potentials of the gray-scale voltages V.sub.0, V.sub.2, V.sub.5 and V.sub.7 during the negative drive time period. It is noted that, in FIG. 2, the gray-scale voltage V.sub.0 having a maximum potential difference with respect to the common electrode voltage V.sub.COM (and corresponding to the gray-scale data "0"), the gray-scale voltage V.sub.7 having a minimum potential difference with respect to the common electrode voltage V.sub.COM (and corresponding to the gray-scale data "7") and the gray-scale voltages V.sub.2 and V.sub.5 having potentials intermediate between the potentials of V.sub.0 and V.sub.7 (and corresponding to the gray-scale data "2" and "5", respectively) are selectively shown from the eight gray-scale voltages V.sub.0 through V.sub.7, and the other gray-scale voltages V.sub.1, V.sub.3, V.sub.4 and V.sub.6 are omitted.
LS denotes a latch strobe signal which is an output pulse synchronous with the horizontal synchronizing signal Hsync. In response to the signal LS, the image data in the sampling memory M.sub.SMP is retrieved into the holding memory M.sub.H, and is simultaneously output to the output circuit section OPC.
Moreover, the AC drive shown in FIG. 2 is performed in accordance with a row inversion drive method (also called a "line inversion drive method") in which the positive and the negative drive time periods alternate on the basis of one row (i.e., one gate line) of a liquid crystal display panel. In this case, considering each row, the waveform of each gray-scale voltage is determined such that the positive and negative polarities of each gray-scale voltage are inverted on a frame (i.e., a vertical interval) basis. That is to say, the waveform of each gray-scale voltage is inverted in synchronism with both the horizontal synchronizing signal Hsync and the vertical synchronizing signal Vsync.
FIG. 3 shows the waveform of the gray-scale voltage V.sub.0 over two frames. The vertical synchronizing signal Vsync is used for defining one frame (vertical interval) and the horizontal synchronizing signal Hsync is used for defining one horizontal interval. As can be understood from FIG. 3, the polarity of the gray-scale voltage V.sub.0 is inverted every horizontal interval within one frame, and the polarity of the gray-scale voltage V.sub.0 during a horizontal interval in the former frame is inverse of the polarity of the gray-scale voltage V.sub.0 during the corresponding horizontal interval in the latter frame.
In accordance with a conventional drive method, as shown in FIG. 2, the leading edge of the output pulse LS is synchronous with the time at which the level of the gray-scale voltage is changed. This is a condition necessarily determined by the fact that output of new data is started in response to the output pulse LS. As a result, the ratio of the length of a time period during which a desired voltage is output from the driver to the data line to the entire length of a positive/negative drive time period can be maximized.
FIG. 4 shows the waveform of a voltage W.sub.0 to be output from a unit driver circuit to a data line over two frames (vertical intervals) in the case of writing display data "0" onto a pixel and the waveform of a voltage W.sub.07 to be output from the unit driver circuit to the data line over two frames (vertical intervals) in the case of alternately writing the display data "0" and display data "7" onto the pixel, together with the waveforms of the horizontal synchronizing signal Hsync and the vertical synchronizing signal Vsync.
In FIG. 4, Va denotes an average voltage of the output voltage W.sub.0 in one frame period. As shown in FIG. 4, in the case of writing the display data "0" onto the pixel, the average voltage Va is constant in two adjacent frames.
In FIG. 4, Va1 denotes an average voltage of the output voltage W.sub.07 in the first frame of the two successive frames, while Va2 denotes an average voltage of the output voltage W.sub.07 in the second frame of the two successive frames. As shown in FIG. 4, in the case of alternately writing the display data "0" and the display data "7" onto the pixel, the average voltages are different from each other in the two adjacent frames. It is noted that .DELTA.Va(+) denotes the magnitude of a positive voltage differential of the average voltage Va1 of the output voltage W.sub.07 with respect to the average voltage Va of the output voltage W.sub.0, while .DELTA.Va(-) denotes the magnitude of a negative voltage differential of the average voltage Va2 of the output voltage W.sub.07 with respect to the average voltage Va of the output voltage W.sub.0. As shown in FIG. 4, in the case of alternately writing the display data "0" and the display data "7" onto the pixel, the average voltage of the output voltages is variable in each frame, i.e., becomes either positive or negative with respect to the average voltage Va.
FIG. 5A shows an equivalent circuit corresponding to one pixel. In FIG. 5A, C.sub.LC denotes a capacitance determined by a pixel electrode, a common electrode and liquid crystal molecules which are dielectric existing therebetween. C.sub.LC is called a "pixel capacitance". The potential difference between the electrodes of a capacitor formed by the pixel capacitance C.sub.LC becomes a voltage actually applied to the liquid crystal molecules. C.sub.S denotes an auxiliary capacitance, and C.sub.qd denotes a stray capacitance to be generated by the gate electrode and the drain electrode of a TFT functioning as a switching element. It is noted that the auxiliary capacitance C.sub.S may be formed by various structures. For example, the auxiliary capacitance C.sub.S may be formed by an electrode connected to a pixel electrode and an electrode at a common electrode potential.
The transmittance of the liquid crystal molecules is determined based on a potential difference between the pixel electrode and the common electrode. Thus, in the OFF period of the TFTs during which a voltage is actually applied to the liquid crystal molecules, the charge of the capacitance C.sub.LC is required to be constant. In the equivalent circuit of the pixel shown in FIG. 5A, it is the potential of the common electrode and that of the gate line of the pixel that affect the charge of the capacitance C.sub.LC. This means that the potential of the data line is excluded from the factors affecting the display quality.
Therefore, when the OFF period of an ideal TFT is discussed, the potential of the data line is regarded as not affecting the display quality irrespective of whether the average voltages of the voltages output to the data line are constant in successive frames (for example, the case of the output voltage W.sub.0 shown in FIG. 4) or different from each other in the successive frames (for example, a case of the output voltage W.sub.07 shown in FIG. 4).
As described above, in a conventional drive method, the potential of the data line has been regarded as not affecting the potential of the pixel electrode after the TFT has been turned OFF. In other words, the OFF resistance of a TFT functioning as a switching element has been regarded as being infinity and the capacitance of the TFT has been regarded as being zero. Of course, a real TFT cannot be in such an ideal state, because the values of the OFF resistance and the capacitance are limited in a real TFT. Thus, a real TFT may affect the display quality. The degree to which the display quality is affected by the TFT depends upon the material and the structure of the TFT. When the display quality is affected to a large degree, the drive timing, the drive waveform and the like, which have been determined while supposing the equivalent circuit shown in FIG. 5A, are required to be corrected in a certain manner.
FIG. 5B shows an equivalent circuit corresponding to one pixel when the OFF resistance and the source-drain capacitance of the TFT itself have been taken into consideration. As can be seen from FIG. 5B, the potential of the data line affects the amount of charge in an electrode (i.e., the pixel electrode), which is closer to the TFT, of the capacitance C.sub.LC via the OFF resistance Roff and the source-drain capacitance C.sub.sd. It is impossible to determine without reserve the specific level of the OFF resistance Roff and the specific magnitude of the source-drain capacitance C.sub.sd which make the degradation in display quality non-negligible.
Specifically, the degree of degradation depends not only on the liquid crystal material of the display medium and the number of gray-scale tones to be displayed, but also on the display pattern. Thus, since the degree of degradation also depends the application of the display device, an absolute criterion for determining the degree of degradation does not exist.
Hereinafter, exemplary defects resulting from the source-drain capacitance C.sub.sd of a TFT as is generated in a conventional drive method will be described with reference to FIGS. 6A and 6B.
FIG. 6A shows a screen on which display patterns having a non-negligible defect resulting from the source-drain capacitance C.sub.sd of a TFT are displayed. In a central window region E, a uniform display pattern having a luminance corresponding to the display data "7" is displayed. On the other hand, in each of the peripheral regions A, B, C and D surrounding the window region E, a checkered pattern, in which display patterns having a luminance corresponding to the display data "0" and display patterns having a luminance corresponding to the display data "7" alternately appear in the respective pixels, is displayed as shown in FIG. 6B.
If such checkered patterns are displayed, each of the peripheral regions C and D, located above and below the window region E, respectively, has non-uniform luminance values over the entire region. The reason is as follows. Since the average data line potential inside the window region E becomes different from that outside the window region E, the pixel electrode potential is affected by the average data line potential in a different manner in these two types of regions.
FIG. 7 shows the waveform of a voltage output from a unit driver circuit to a data line DL and the variation of the average of the voltage over two frame periods when display patterns such as those shown in FIG. 6A are displayed. The data line DL passes the window region E and the peripheral regions C and D. Herein, it is assumed that the unit driver circuit alternately outputs a positive voltage and a negative voltage, corresponding to the same gray-scale tone, to the data line DL during a retrace interval. It is noted that the specific waveform of the voltage output from the unit driver circuit to the data line DL during the retrace interval is omitted, but the average of the voltage is shown instead.
In order to evaluate the influence of the potential of the data line DL upon the respective pixels, it is necessary to determine the difference among the potentials of all of the time periods t1 through t4'.
First, a pixel located at a position X within the region C shown in FIG. 6A (hereinafter, such a pixel will be referred to as pixel X) will be considered. Assuming that the pixel X is charged to have a first polarity during a horizontal interval x included in a frame (see FIG. 7), the pixel X is charged to have a second polarity inverse of the first polarity during a corresponding horizontal interval x' included in the next frame (see FIG. 7).
The difference between the average potential of the data line DL and the potential of the pixel X is small in a remaining time period succeeding the horizontal interval x of the time period t1 and all through the time period t3. Thus, the influence of potential of the data line DL is less significant during these time periods. On the other hand, the difference between the average potential of the data line DL and the potential of the pixel X is large in a time period preceding the horizontal interval x' of the time period t1'. Thus, the influence of the potential of the data line DL is significant during this time period.
During the time period t1 (more exactly, the time period succeeding the horizontal interval x), the time period t3 and the time period t1' (more exactly, the time period preceding the horizontal interval x'), the drop of the potential of the pixel X with respect to the common electrode potential is equal to that of the potential of the pixels located within the regions A and B and on the same scanning line as that of the pixel X (see W.sub.07 shown in FIG. 4). Thus, the pixel X and the corresponding pixels within the regions A and B are affected by the potential of the data line DL to the same degree.
During the time period t2, the average potential of the data line DL is the central potential of the positive and the negative gray-scale voltages. Thus, in the time period t2, the drop of the potential of the pixel X with respect to the common electrode potential is larger than that of the potential of the pixels located within the regions A and B and on the same scanning line as the pixel X. This is because, in the regions A and B, the average potential of the data line during the time period t2 is equal to the average potential of the data a line during the time periods t1 and t3.
The time period t4 is a retrace interval. In the time period t4, the drop of the potential of the pixel X with respect to the common electrode potential is equal to that of the potential of the pixels located within the regions A and B and on the same scanning line as the pixel X. Thus, the pixel X and the corresponding pixels within the regions A and B are affected by the potential of the data line DL to the same degree.
Because of the above-described reasons, during a time period from the horizontal interval x until the horizontal interval x', the gray-scale tone in the region C above the window region E is observed as being lighter than the gray-scale tones observed in the regions A and B. The above description is also applicable to the time period from the horizontal interval x' until the horizontal interval x.
Next, a pixel located at a position Y within the region D shown in FIG. 6A (hereinafter, such a pixel will be referred to as a pixel Y) will be considered.
The difference between the average potential of the data line DL and the potential of the pixel Y is large in the time period t1' and a remaining time period preceding the horizontal interval y' of the time period t3'. Thus, the influence of the potential of the data line DL is significant during these time periods. On the other hand, the difference between the average potential of the data line DL and the potential of the pixel Y is small in a time period succeeding the horizontal interval y of the time period t3. Thus, the influence of the potential of the data line DL is less significant during this time period.
During the time period t3 (more exactly, the time period succeeding the horizontal interval y), the time period t1' and the time period t3' (more exactly, the time period preceding the horizontal interval y'), the drop of the potential of the pixel Y with respect to the common electrode potential is equal to that of the potential of the pixels located within the regions A and B and on the same scanning line as the pixel Y. Thus, the pixel Y and the corresponding pixels within the regions A and B are affected by the potential of the data line DL to the same degree.
During the time period t2', the average potential of the data line DL is the central potential of the positive and the negative gray-scale voltages. Thus, in the time period t2', the drop of the potential of the pixel Y with respect to the common electrode potential is smaller than that of the potential of the pixels located within the regions A and B and on the same scanning line as the pixel Y. This is because, in the regions A and B, the average potential of the data line during the time period t2' is equal to the average potential of the data line during the time periods t1' and t3'.
The time period t4 is a retrace interval. In the time period t4, the drop of the potential of the pixel Y with respect to the common electrode potential is equal to that of the potential of the pixels located within the regions A and B and on the same scanning line as the pixel Y. Thus, the pixel Y and the corresponding pixels within the regions A and B are affected by the potential of the data line DL to the same degree.
Because of the above-described reasons, during a time period from the horizontal interval y until the horizontal interval y', the gray-scale tone in the region D below the window region E is observed as being deeper than the gray-scale tones observed in the regions A and B. The above description is also applicable to the time period from the horizontal interval y' until the horizontal interval y.
The gray-scale tones are varied in the regions C and D of FIG. 6A owing to the above-described potential variations.